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MC14532B 8-Bit Priority Encoder
The MC14532B is constructed with complementary MOS (CMOS) enhancement mode devices. The primary function of a priority encoder is to provide a binary address for the active input with the highest priority. Eight data inputs (D0 thru D7) and an enable input (Ein) are provided. Five outputs are available, three are address outputs (Q0 thru Q2), one group select (GS) and one enable output (Eout).
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16 PDIP-16 P SUFFIX CASE 648 MC14532BCP AWLYYWW 1
* Diode Protection on All Inputs * Supply Voltage Range = 3.0 Vdc to 18 Vdc * Capable of Driving Two Low-power TTL Loads or One Low-Power
Schottky TTL Load over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 3.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value - 0.5 to +18.0 - 0.5 to VDD + 0.5 10 500 - 55 to +125 - 65 to +150 260 Unit V V mA mW C C C SOIC-16 D SUFFIX CASE 751B
16 14532B AWLYWW 1 16 SOEIAJ-16 F SUFFIX CASE 966 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week MC14532B AWLYWW
2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
ORDERING INFORMATION
Device MC14532BCP MC14532BD MC14532BDR2 MC14532BF MC14532BFEL MC14532BFR1 Package PDIP-16 SOIC-16 SOIC-16 SOEIAJ-16 SOEIAJ-16 SOEIAJ-16 Shipping 2000/Box 48/Rail 2500/Tape & Reel See Note 1. See Note 1. See Note 1.
v
v
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
(c) Semiconductor Components Industries, LLC, 2000
1
March, 2000 - Rev. 3
Publication Order Number: MC14532B/D
MC14532B
PIN ASSIGNMENT
D4 D5 D6 D7 Ein Q2 Q1 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Eout GS D3 D2 D1 D0 Q0
TRUTH TABLE
Input Ein 0 1 1 1 1 1 1 1 1 1 D7 X 0 1 0 0 0 0 0 0 0 D6 X 0 X 1 0 0 0 0 0 0 D5 X 0 X X 1 0 0 0 0 0 D4 X 0 X X X 1 0 0 0 0 D3 X 0 X X X X 1 0 0 0 D2 X 0 X X X X X 1 0 0 D1 X 0 X X X X X X 1 0 D0 X 0 X X X X X X X 1 GS 0 0 1 1 1 1 1 1 1 1 Q2 0 0 1 1 1 1 0 0 0 0 Output Q1 0 0 1 1 0 0 1 1 0 0 Q0 0 0 1 0 1 0 1 0 1 0 Eout 0 1 0 0 0 0 0 0 0 0
X = Don't Care
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- 0.1 -- 5.0 10 20 - 2.4 - 0.51 - 1.3 - 3.4 0.51 1.3 3.4 -- -- -- -- -- - 4.2 - 0.88 - 2.25 - 8.8 0.88 2.25 8.8 0.00001 5.0 0.005 0.010 0.015 -- -- -- -- -- -- -- 0.1 7.5 5.0 10 20 - 1.7 - 0.36 - 0.9 - 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- - 55_C 25_C 125_C Max Min -- -- -- Typ (4.) 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current (5.) (6.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD Adc pF Adc IT IT = (1.74 A/kHz) f + IDD IT = (3.65 A/kHz) f + IDD IT = (5.73 A/kHz) f + IDD Adc 4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 5. The formulas given are for the typical characteristics only at 25_C. 6. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.005.
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MC14532B
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SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)
Characteristic Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Propagation Delay Time -- Ein to Eout tPLH, tPHL = (1.7 ns/pF) CL + 120 ns tPLH, tPHL = (0.66 ns/pF) CL + 77 ns tPLH, tPHL = (0.5 ns/pF) CL + 55 ns Propagation Delay Time -- Ein to GS tPLH, tPHL = (1.7 ns/pF) CL + 90 ns tPLH, tPHL = (0.66 ns/pF) CL 57 ns tPLH, tPHL = (0.5 ns/pF) CL + 40 ns Propagation Delay Time -- Ein to Qn tPLH, tPHL = (1.7 ns/pF) CL + 195 ns tPLH, tPHL = (0.66 ns/pF) CL + 107 ns tPLH, tPHL = (0.5 ns/pF) CL + 75 ns Propagation Delay Time -- Dn to Qn tPLH, tPHL = (1.7 ns/pF) CL + 265 ns tPLH, tPHL = (0.66 ns/pF) CL + 137 ns tPLH, tPHL = (0.5 ns/pF) CL + 85 ns Propagation Delay Time -- Dn to GS tPLH, tPHL = (1.7 ns/pF) CL + 195 ns tPLH, tPHL = (0.66 ns/pF) CL + 107 ns tPLH, tPHL = (0.5 ns/pF) CL + 75 ns Symbol tTLH, tTHL VDD 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ (8.) 100 50 40 205 110 80 175 90 65 280 140 100 300 170 110 280 140 100 Max 200 100 80 410 220 160 ns 350 180 130 ns 560 280 200 ns 600 340 220 ns 560 280 200 Unit ns tPLH, tPHL ns tPLH, tPHL tPHL, tPLH tPLH, tPHL tPLH, tPHL 7. The formulas given are for the typical characteristics only at 25_C. 8. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. Vout Ein D0 D1 SWITCH MATRIX D2 D3 D4 D5 D6 D7 EXTERNAL POWER SUPPLY VGS = VDD VDS = Vout Sink Current D0 thru D7 X X X X X Ein 0 0 0 0 0 VGS = - VDD VDS = Vout - VDD Source Current D0 thru D6 0 0 0 0 0 D7 0 1 1 1 1 Ein 1 1 1 1 1 PULSE GENERATOR (fo) Eout Q0 Q1 Q2 GS VDD ID 500 F ID 0.01 F Ein D0 D1 D2 D3 D4 D5 D6 D7 VSS GS CL Eout CL Q0 CL Q1 CL Q2 CL Output Under Test Eout Q0 Q1 Q2 GS
Figure 1. Typical Sink and Source Current Characteristics
Figure 2. Typical Power Dissipation Test Circuit
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MC14532B
VDD Ein D0 D1 PROGRAMMABLE PULSE GENERATOR D2 D3 D4 D5 D6 D7 GS VSS CL Eout CL Q0 CL Q1 CL Q2 CL
NOTE: Input rise and fall times are 20 ns PIN NO. D0 D1 D2 D3 D4 D5 D6 D7 Ein 10 11 12 13 1 2 3 4 5 50% 50% 50% tPLH 90% 50% 10% tTLH tTHL tPLH tPHL 90% 50% 10% tTHL tPHL 90% 50% 10% tTHL tPHL 90% 50% 10% tTHL tPHL 90% 50% 10% tTHL tPHL 50% 50% 50% 50% 50% 50%
Eout
15
GS
14
tTLH tPLH
tPLH tPHL
tPLH tPHL
tPLH tPHL
Q0
9
tPLH tPHL
tPLH
tTLH
Q1
7 tPLH tTLH
Q2
6
tTLH
Figure 3. AC Test Circuit and Waveforms
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MC14532B
LOGIC DIAGRAM (Positive Logic)
LOGIC EQUATIONS
Eout = Ein D0 D1 D2 D3 D4 D5 D6 D7 Q0 = Ein (D1 D2 D4 D6 + D3 D4 D6 + D5 D6 + D7) Q1 = Ein (D2 D4 D5 + D3 D4 D5 + D6 + D7) 10 D0 Q2 = Ein (D4 + D5 + D6 + D7) GS = Ein (D0 + D1 + D2 + D3 + D4 + 05 + D6 + D7) 11 D1
9 Q0
12 D2
13 D3
1 D4 7 Q1 2 D5
3 D6
4 D7
6 5 Ein 14 GS Q2
15 Eout
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D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D7 VDD Ein GS
D6
D5
D4
D3
D2
D1
D0 Eout
D7 Ein
D6
D5
D4
D3
D2
D1
D0 Eout Eout = "1" WITH Din = "0"
Q2 Q1
Q0
Q2 Q1
Q0
3/4 MC14071B
Q3
Q2
Q1
Q0
Figure 4. Two MC14532B's Cascaded for 4-Bit Output
VDD
VSS
CLOCK INPUT C E 1/2 MC14520B Q1 Q2 Q3 Q4 Q1 R C Q2 E 1/2 MC14520B Q3 Q4 R
DIGITAL TO ANALOG CONVERSION
The digital eight-bit word to be converted is applied to the inputs of the MC14512 with the most significant bit at X7 and the least significant bit at X0. A clock input of up to 2.5 MHz (at VDD = 10 V) is applied to the MC14520B. A compromise between Ibias for the MC1710 and R between N and P-channel outputs gives a value of R of 33 k ohms. In order to filter out the switching frequencies, RC should be about 1.0 ms (if R = 33 k ohms, C 0.03 F). The analog 3.0 dB bandwidth would then be dc to 1.0 kHz.
[
DIGITAL INPUT/OUTPUT D0 D1 D2 D3 D4 D5 D6 D7 VDD Ein Q2 Q1 Q0 A B C X7 X6 X5 X4 X3 X2 X1 X0 MC14512 Z R ANALOG OUTPUT C 8-BIT WORD TO BE CONVERTED
ANALOG TO DIGITAL CONVERSION
An analog signal is applied to the analog input of the MC1710. A digital eight-bit word known to represent a digitized level less than the analog input is applied to the MC14512 as in the D to A conversion. The word is incremented at rates sufficient to allow steady state to be reached between incrementations (i.e. 3.0 ms). The output of the MC1710 will change when the digital input represents the first digitized level above the analog input. This word is the digital representation of the analog word.
MC1710 STOP WORD INCREMENTATION ANALOG INPUT
Figure 5. Digital to Analog and Analog to Digital Converter
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MC14532B
PACKAGE DIMENSIONS
-A-
16 9
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
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MC14532B
PACKAGE DIMENSIONS
-A-
SOIC-16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
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MC14532B
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O
LE Q1 E HE
1 8
16
9
M_ L DETAIL P
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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Notes
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MC14532B
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MC14532B/D

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